Roadmap#
This page tracks which language and HAL features have been implemented, and what is planned next.
Implemented#
Language#
Feature |
Notes |
|---|---|
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Compile-time DCE on |
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Runtime or compile-time bound; |
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Fixed-size array or constant list literal |
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Compile-time index counter |
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Compile-time unroll over paired lists |
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Compile-time reverse unroll |
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Literal, wildcard, OR ( |
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Typed params, defaults, keyword args, overloading by type, tuple multi-return |
Top-level scripts (no |
Compiler synthesizes |
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ZCA |
Single-level class inheritance |
ZCA base + derived; |
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Zero-cost integer constants; no SRAM |
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Compile-time only; statically false → CompileError |
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Cross-function variable access; |
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AVR only; |
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Compile-time fold on constant list; runtime equality chain |
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Maps to |
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Returns |
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Reinterpret raw bytes as |
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Compile-time: |
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Compile-time fold or unrolled chain |
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Compile-time constant fold |
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Treated as |
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Mutable SRAM buffer |
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Compile-time fold or runtime |
Raw strings |
No escape processing |
Extended unpacking |
Compile-time tuples only (PEP 3132) |
Nested list comprehensions |
Full outer × inner product unroll; |
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CT unroll of ZCA instance arrays from list comprehensions; plain for-in and enumerate both supported |
Slice indexing |
Compile-time constant indices |
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Inlined as anonymous |
Dunder operator overloading |
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External C/C++ symbol interop with AVR ABI |
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Compile-time guard; body promoted in main, eliminated in libs |
Triple-quoted strings |
Multiline string literals; leading newline after opening quote stripped; useful for multiline |
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MCU extensions#
Feature |
Notes |
|---|---|
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Required annotation for all variables |
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Maps to |
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Memory-mapped I/O |
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Compile-time constants; flash-resident arrays via |
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Inline assembly with register constraints |
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Intrinsic busy-wait |
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Timer0 overflow; atomic 32-bit read under CLI/SEI |
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Zero-cost expansion |
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ISR handler generation with automatic |
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Compile-time expansion |
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Conditional compilation by chip name / architecture |
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Compile-time clock frequency in Hz |
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C/C++ interop: |
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IEEE 754 single-precision; AVR only; uses |
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No compiler prolog/epilog; registers hold raw calling-convention values at function entry; required for precise |
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Silently ignored — all class methods in PyMCU are effectively static |
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HAL (ATmega328P)#
Module |
Coverage |
|---|---|
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Drivers#
Module |
Device |
|---|---|
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DHT11 temperature + humidity |
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DS18B20 1-Wire precision temperature (12-bit) |
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LM35 analog temperature (ADC) |
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HD44780 LCD (4-bit parallel) |
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SSD1306 OLED (I2C, 128×64) |
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MAX7219 7-segment display (SPI) |
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BMP280 barometer (I2C) |
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WS2812 NeoPixel |
Compatibility layers#
Package |
Activation |
Coverage |
|---|---|---|
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Boards#
Module |
Pins |
|---|---|
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RP2040 (alpha)#
The RP2040 (Raspberry Pi Pico, ARM Cortex-M0+) backend is implemented in alpha.
The reason is philosophical: the RP2040 is the most popular MicroPython target today. PyMCU’s promise is prototype fast in MicroPython, bring to the metal with PyMCU — the same source file that runs on a Pico under MicroPython should compile to bare-metal firmware with zero runtime when you are ready to ship. RP2040 closes that loop for the largest audience of MicroPython users.
Unlike the AVR/PIC/RISC-V backends, the RP2040 backend does not emit assembly
directly. It lowers PyMCU’s architecture-agnostic IR to LLVM IR, so LLVM handles
register allocation, instruction selection, the AAPCS calling convention and all
optimization passes for thumbv6m-none-eabi. pymcu build produces a flat flash
image (firmware.bin); the build is verified end-to-end against the RP2040Sharp
emulator (pip install pymcu[rp2040], requires LLVM on the host).
Feature |
Status |
|---|---|
GPIO ( |
✅ Single-cycle IO (SIO); zero-cost; all 30 GPIOs |
UART0 ( |
✅ PL011; compile-time baud divisors |
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✅ Hardware TIMER (1 MHz); accurate on silicon |
Single core (core 0) |
✅ |
Dual-core / SIO FIFO |
⏳ Planned |
PIO, SPI, I2C, PWM, ADC, USB |
⏳ Planned |
GC ( |
⏳ Not yet on this backend |
Planned#
Feature |
Notes |
|---|---|
RP2040 peripherals |
SPI / I2C / PWM / ADC / PIO / USB; dual-core launch |
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Fixed-point arithmetic without soft-float overhead; |
MicroPython/CircuitPython API alignment |
Broaden compat module coverage; close remaining API gaps |
PIC18 codegen |
Extend backend for PIC18Fxxxx family |
RISC-V 32-bit codegen |
CH32V003, ESP32-C3 targets |
RP2040 PIO backend |
Programmable I/O state machine output |
Over-the-air (OTA) support |
Bootloader + |
ARM Cortex-M3/M4 codegen |
STM32, nRF52 — reuses the LLVM backend |
Not planned#
Feature |
Reason |
|---|---|
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Dynamic hash tables require heap; no runtime |
Garbage collection beyond |
Full GC incompatible with deterministic ISR timing |
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Use |
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Use |
Closures capturing mutable vars |
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Requires heap |
Multiple inheritance |
Complexity vs. benefit for ZCA model |
Reflection / |
No runtime type info |
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No interpreter on MCU |